Day1: Vivado XDC and STA
The new Vivado® tools Suite use a common data model throughout the FPGA design proces. This yields run-time and memory resource benefits. This new Design System Environment allows the design and verification of high complex FPGAs. The integrated scripting support allows the users to design their FPGAs using the project-based or the non-project batch design flows.
Unlike the ISE tools, the Vivado tools set use a common constraint language (XDC) throughout the FPGA design process. This enables synthesis optimization as well as timing optimizations significantly better than the ISE software.
This one day introduction seminar addresses FPGA designer with no or little specific knowledge of design optimization techniques. The attendee will learn how to define the timing constraints (XDC) as well as how to identify and fix potential timing issues after the implementation using the timing analyzer (STA).
Day2: ZYNQ-7000 EPP
Based on the Xilinx All programmable SoC architecture, the Zynq®-7000 All Programmable SoCs enable extensive system level differentiation, integration, and flexibility through hardware, software, and I/O programmability.
Using the Zynq-7000 platform, you can design smarter systems with tightly coupled software based control and analytics with real time hardware-based processing and optimized system interfaces — with vastly lower BOM costs, lower NRE costs, lower design risk, and of course much faster time to market. All Zynq devices are optimized for specific combinations of system power, cost, and size to meet the needs of smarter control, smarter vision and smarter networks.
This one day introduction seminar addresses FPGA designer with no or little specific knowledge of Embedded System Design. After introduction to the ZYNQ-700 EPP architecture the attendee will learn how to configure his embedded system and how to use the IP Integrator as well as the Software Development Kit (SDK) to successfully design ZYNQ based embedded systems.
Xilinx 7-Series / UltraScale / UltraScale+ FPGAs
Basic knowledge of FPGAs and HDL is helpful but not required.
Basic knowledge of embedded design / C is helpful but not required.
PLC2 / ELECTRA IC
For detailed agenda of the seminar visit www.electraic.com